| 摘要 |
Described herein is a row decoder (5) for a phase-change memory device (1) provided with an array (2) of memory cells (3) organized according to a plurality of array wordlines (WL<i>) and array bitlines (BL); the row decoder (5) has a hierarchical architecture and has a global decoder (8; 8') that addresses a first (MWL_LV; MWL') and a second (MWL; MWL_WR) global wordline according to first address signals (GP, D); and at least one local decoder (9; 9'), which is operatively coupled to the global decoder (8; 8') and addresses a respective array wordline (WL<i>) according to the value of the first global wordline and the second global wordline and of second address signals (WLSEL, WLSELN_LV; WLSEL_SW). The local decoder (9; 9') has a first circuit branch (25, 26, 31; 40, 41) generating, when the first global wordline (MWL_LV; MWL') is addressed, a first current path between the array wordline (WL<i>) and a first biasing source (V DD ) during a reading operation; and a second circuit branch (32; 42) generating, when the second global wordline (MWL_LV; MWL') is addressed, a second current path, distinct from the first current path, between the array wordline (WL<i>) and a second biasing source (V CC ) during a programming operation. |
