发明名称
摘要 There is provided a processor operable in a first domain and a second domain, the processor comprising: monitoring logic operable to monitor the processor and capture diagnostic data; a storage element operable to contain at least one control parameter; control logic operable to control the monitoring logic in dependence on the at least one control parameter and the domain in which the processor is operating, to suppress capturing of diagnostic data relating to predetermined activities of the processor in the first domain. In some embodiments the first domain is a secure domain and the second domain is a non-secure domain, the monitoring function being debug or trace.
申请公布号 JP4423012(B2) 申请公布日期 2010.03.03
申请号 JP20030386048 申请日期 2003.11.17
申请人 发明人
分类号 G06F9/46;G06F12/14;G06F9/48;G06F11/28;G06F11/30;G06F17/40;G06F21/71;H04L9/00 主分类号 G06F9/46
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