发明名称 Pipeline architecture for maximum a posteriori (MAP) decoders
摘要 <p>The application relates to sliding-window maximum a posteriori MAP decoding. In a MAP decoder, a method for determining binary states of received signals comprises receiving data bits, each bit being accompanied by at least one parity bit, providing each received data bit and parity bit with an address (16a) of a calculated extrinsic value (14a) and associated intrinsic data and storing the data bits, the parity bits and the extrinsic value address in a first memory (12).</p>
申请公布号 EP2159921(A2) 申请公布日期 2010.03.03
申请号 EP20090010052 申请日期 2002.04.15
申请人 INTERDIGITAL TECHNOLOGY CORPORATION 发明人 HEPLER, EDWARD L.;STARSINIC, MICHAEL F.
分类号 G06F11/10;H03M13/39;H03M13/29;H03M13/45 主分类号 G06F11/10
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