发明名称 Metal interconnect structure and process for forming same
摘要 A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on a substrate, and a conductor embedded in the dielectric layer, the conductor having an edge portion with an inwardly rounded shape.
申请公布号 US7670947(B2) 申请公布日期 2010.03.02
申请号 US20070652077 申请日期 2007.01.11
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 WU TSANG-JIUH;JANG SYUN-MING;LIANG MING-CHUNG;TSAI HSIN-YI
分类号 H01L21/4763;H01L21/311 主分类号 H01L21/4763
代理机构 代理人
主权项
地址
您可能感兴趣的专利