发明名称 |
Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing |
摘要 |
A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
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申请公布号 |
US7671362(B2) |
申请公布日期 |
2010.03.02 |
申请号 |
US20070953568 |
申请日期 |
2007.12.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;ADVANCED MICRO DEVICES, INC. (AMD) |
发明人 |
BOLOM TIBOR;CHANDA KAUSHIK;FILIPPI RONALD G.;GRUNOW STEPHAN;MCLAUGHLIN PAUL S.;SANKARAN SUJATHA;SIMON ANDREW H.;STANDAERT THEODORUS E.;WERKING JAMES |
分类号 |
H01L23/58 |
主分类号 |
H01L23/58 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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