摘要 |
Methods and circuits to reduce jitter in a design block including partitioning the design block. A circuit design is partitioned into multiple partitioned design blocks performing the same task as the original circuit deign. In one embodiment, a core clock signal is supplied to each of the partitioned design blocks, having a frequency higher than frequency of the reference clock signal. Additionally each of the partitioned design blocks receives a mutually exclusive enable signal, where each of the partitioned design blocks may be activated once at a given time.
|