发明名称 SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME
摘要 A leakage power recovery system and method, and a electronic design automation (EDA) tool incorporating either or both of the system and the method. In one embodiment, the timing signoff tool includes: (1) a power recovery module configured to make first conditional replacements of cells in at least one path in a circuit design with lower leakage cells and estimate a delay and a slack of the at least one path based on the first conditional replacement and (2) a speed recovery module associated with the power recovery module and configured to determine whether the first conditional replacements cause a timing violation with respect to the at least one path and make second conditional replacements with higher leakage cells until the timing violation is removed.
申请公布号 US2010050144(A1) 申请公布日期 2010.02.25
申请号 US20080198030 申请日期 2008.08.25
申请人 LSI CORPORATION 发明人 ZAHN BRUCE E.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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