| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that implements a smart power-down mode of a DLL circuit to stably generate a clock, and also to provide a method of controlling the same. <P>SOLUTION: A semiconductor integrated circuit includes: a DLL control means configured to generate a buffer enable signal, the buffer enable signal being a pulse signal that is periodically enabled when a smart power down signal is enabled; and a DLL circuit configured to control a phase of an external clock signal in response to the buffer enable signal to generate an output clock. <P>COPYRIGHT: (C)2010,JPO&INPIT |
