| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data capture circuit, wherein high-speed data capture is performed stably and low power consumption is attained. Ž<P>SOLUTION: The data capture circuit includes: a comparator CMP1, in which a clock signal CKP and the opposite phase signal CKN of the clock signal CKP are input, and the same phase clock signal CLP1 as the clock signal CKP and the opposite phase clock signal CLN1 are output; a comparator CMP2, in which the clock signal CLP1 is input to a non-inversion input terminal, and the clock signal CLN1 is input to an inversion input terminal; and a comparator CMP3, in which the clock signal CLP1 is input to the inversion input terminal, and the clock signal CLN1 is input to the non-inversion input terminal, wherein by using output signals CL1, CL2 of the comparators CMP2, CMP3 as clock signals of latch circuits L1, L2, the rise times or delay times of rise of clock signals CL1, CL2 input to the latch circuits L1, L2 are made to be the same extent and the data capture circuit with low power consumption is attained. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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