| 摘要 |
A fault-tolerant processor device including a master processor and a plurality of operationally coupled slave processors. The master processor sends a command to each of the slave processors to initiate operation to each control a different one of a plurality of operations during fault-free operation. The master processor monitors each of the operations to confirm the fault-free operation. In a case wherein fault-free operation is not confirmed, the master processor identifies a faulty one of the slave processors, disables the faulty slave processor and initiates operation of a fault-free one of the slave processors to control the operations of the faulty slave processor in addition to the operations of the fault-free slave processor. If the master processor determines that both of the slave processors are faulty, the master processor may disable both of the slave processors and control each of the operations independent of the faulty slave processors.
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