| 摘要 |
A semiconductor memory device includes a plurality of memory cells 205 provided corresponding to nodes of a plurality of word lines (WLBk, WLBk+1) and a plurality of bit line pairs (D1, DB1, D1+1, DB1+1). And column selection lines (S1, S1+1) are provided corresponding to each of the bit line pairs. Each of the memory cell includes an inverter (INV3) receiving power from the column selection line, and having its input connected to the word line and its output connected to gates of access transistors. Only the access transistors of a memory cell whose word line and column selection line are simultaneously selected are turned on.
|
