| 摘要 |
<p>A memory cell (300) is configured so that it is equipped with a semiconductor substrate (301); a variable resistance element (309) that consists of a lower electrode (309a), an upper electrode (309c), and a variable resistance layer (309b), the resistance value of which reversibly changes based on the application of voltage signals of different polarities across the two electrodes; and an N-type MOS transistor (317) configured on the main surface of the semiconductor substrate (301), wherein the variable resistance layer (309b) comprises an oxygen-depleted transition metal oxide layer (309b-1) that contacts the lower electrode (309a) and is composed of MOx, and an oxygen-depleted transition metal oxide layer (309b-2) that contacts the upper electrode (309c) and is composed of MOy (where x<y), and wherein, when a voltage signal with a polarity that increases the resistance of the variable resistance layer (309b) is applied to the transistor (317) and variable resistance element (309), an N-type diffusion layer region (302b) configured as a drain is connected to the lower electrode (309a) so that a substrate bias effect does not occur in the transistor (317).</p> |
| 申请人 |
PANASONIC CORPORATION;MURAOKA, SHUNSAKU;KANZAWA, YOSHIHIKO;MITANI, SATORU;KATAYAMA, KOJI;SHIMAKAWA, KAZUHIKO;FUJII, SATORU;TAKAGI, TAKESHI |
发明人 |
MURAOKA, SHUNSAKU;KANZAWA, YOSHIHIKO;MITANI, SATORU;KATAYAMA, KOJI;SHIMAKAWA, KAZUHIKO;FUJII, SATORU;TAKAGI, TAKESHI |
