| 摘要 |
A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated attributes and a netlist, where the netlist is a synthesized design of the semiconductor chip. The method includes tracking the macro test I/O to a chip test I/O. The method further includes detecting mismatches between attributes associated with the macro test I/O and the chip test I/O. Subsequently, reporting any mismatches between the attributes associated with the macro test I/O and the chip test I/O.
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