发明名称 SYSTEM-IN-PACKAGE WITH THROUGH SUBSTRATE VIA HOLES
摘要 The present invention relates to a system-in-package that comprises an integration substrate with a thickness of less than 100 micrometer and a plurality of through-substrate vias, which have an aspect ratio larger than 5. A first chip is attached to the integration substrate and arranged between the integration substrate and a support, which is suitable for mechanically supporting the integration substrate during processing and handling. The system-in-package can be fabricated according to the invention without a through-substrate-hole etching step. The large aspect ratio implies reduced lateral extensions, which allow increasing the integration density and decreasing lead inductances.
申请公布号 US2010044853(A1) 申请公布日期 2010.02.25
申请号 US20080523053 申请日期 2008.01.14
申请人 NXP, B.V. 发明人 DEKKER RONALD;YANNOU JEAN-MARC;VAN VEEN NICOLAAS J. A.
分类号 H01L23/538;H01L21/50;H05K1/11 主分类号 H01L23/538
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