| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a high-speed variable-length decoder circuit which can obtain a plurality of results of recovery processing, using a single clock. Ž<P>SOLUTION: A plurality of decoder circuits are incorporated, and a controller which compares the number of bits, capable of being recovered by a predetermined one clock with the data of the number of recovered bits output from each decoder circuit is provided and a plurality of decoding processes are eliminated from being kept waiting for other decoding processings that exceed one clock. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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