发明名称 Method and system for semiconductor design hierarchy analysis and transformation
摘要 A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.
申请公布号 US7669158(B2) 申请公布日期 2010.02.23
申请号 US20040955067 申请日期 2004.09.30
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 KAMAT VISHNU GOVIND
分类号 G06F17/50 主分类号 G06F17/50
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