| 摘要 |
A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device includes a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.
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