METHOD FOR COMPLETE REMOVAL OF TRAPPED CHARGES IN THE SOURCE(OR DRAIN) AND BULK REGION OF VERTICAL TRANSISTORS

摘要

PURPOSE: A method for completely removing trapped charges in the source(or drain) and bulk region of vertical transistors is provided to improve the performance of a vertical transistor by improving a switch characteristic of the vertical transistor. CONSTITUTION: Impurity is inserted in the front of substrate. Impurity is activated through rapid thermal processing. The filler or a silicon pillar for the vertical transistor formation is formed in the front side of wafer. The deposited oxide film is planarized on the substrate through chemical mechanical polishing(S911). The oxide film is etched back by dry etching(S929). The thermal oxide film is grown up in the front of substrate(S931). The gate electrode is formed in the front of substrate(S935). The deposited oxide film or nitride film is planarized in the front of substrate with the CMP process(S937). The contact hole is formed in the gate electrode/source/drain region(S947). The contact metal is formed on the contact hole(S951). The metal layer is formed in the front of substrate(S953).