| 摘要 |
A scheme is provided that guarantees the completion of cache invalidation processing in an information processing apparatus that performs directory-based coherence control. Each processor includes a cache and a Fence control unit that transmits an identifier to be returned to its own processor toward each bank through a network at timing when guarantee of completion of consistency processing of data stored in shared memory and the cache is requested and confirms that the identifier is returned from each bank. Each bank includes a memory main body, a directory that issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body, and an invalidation request queue that queues the invalidation request and the identifier and transmits one of the invalidation request and the identifier through the network in a sequence of queuing. |
