发明名称 METHOD AND APPARATUS FOR ADAPTIVE CLOCK PHASE CONTROL FOR LSI POWER REDUCTION
摘要 Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.
申请公布号 US2010039152(A1) 申请公布日期 2010.02.18
申请号 US20080192385 申请日期 2008.08.15
申请人 SONY COMPUTER ENTERTAINMENT INC. 发明人 TAKANO CHIAKI
分类号 H03K5/13 主分类号 H03K5/13
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