发明名称 INTEGRATED CIRCUIT AND METHOD FOR DESIGNING INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To perform testing of an input/output signal line with a module as part of scan testing of the module by applying a simple change to a scan circuit and a scan pattern of the module. Ž<P>SOLUTION: An integrated circuit 50 which includes the module 61 having the scan test circuits 63 to 65, includes a dummy scan FF 66 provided in the vicinity of an input signal line 71 to the module, a dummy output signal line 72 for outputting a normal output of the dummy scan FF, and a selector 56 that is provided at a portion except the module and selects one of an input signal to the input signal line 71 and an output signal from the dummy output signal line. A scan output SO of the dummy scan FF is input to a scan input SI of the scan FF 63 in the module. The scan testing of the module is carried out while inputting the scan input to the dummy scan FF under a condition that the selector selects the output signal from the dummy output signal line. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010038656(A) 申请公布日期 2010.02.18
申请号 JP20080200143 申请日期 2008.08.01
申请人 FUJITSU MICROELECTRONICS LTD 发明人 NEMOTO YUTAKA;OGAWA YOSHIMASA
分类号 G01R31/28;H01L21/82;H01L21/822;H01L27/04 主分类号 G01R31/28
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