| 摘要 |
PROBLEM TO BE SOLVED: To solve the bit slippage of one-bite data read from a storage device in a receiving register of a receiving-side CPU. SOLUTION: When writing data to the storage device, dummy bits, start bit, control code bits and address data bits are serially arranged in this order to form 2-byte control data. The control data is stored in a transmitting register in a unit of 1-byte bit group from the beginning of the serial arrangement, and serially transmitted to the storage device together with synchronous clock signal through a transmitting port. Following the control data, 1-byte transmission data is stored in the transmitting register and serially transmitted to the storage device together with synchronous clock signal. When reading data from the storage device, dummy bits at the beginning of the 2-byte control data are reduced by 1 byte, 1 byte of dummy bits is instead after the tailing bit A0 of the address data, and the dummy bits are arranged at the end of the second byte. COPYRIGHT: (C)2010,JPO&INPIT
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