发明名称 LAMINATED CHIP COMPONENT AND MANUFACTURING METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a laminated chip component which can form a connection portion that vertically links conductor patterns to have a low height and a gentle slope, thus ensuring that the conductor patterns are connected and high reliability is attained, and to provide a manufacturing method therefor. SOLUTION: A chip body is laminated by a print lamination method of alternately recoating insulating pastes (mask layers 5, 7) and conductor pastes (conductor patterns 6, 8). A connecting portion where the conductor patterns 6, 8 are vertically linked is disposed, at a position where a terminal end (projection end 12) of the lower-side conductor pattern 6 lies side-by-side with a starting end (crank end 11) of the upper-layer side conductor pattern 8, with the side edge of the conductor pattern contacting the side edge of the conduct pattern. The crank end 11 is superimposed in a predetermined manner on the projection end 12, thus providing a predetermined overlapped area 13. At the connection portion where the conductor patterns are connected, the side edge of the terminal end contacts that of the starting end, thus resulting in the electrical connection between them and the prevention of increased thickness, in the height direction of the lamination. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010040966(A) 申请公布日期 2010.02.18
申请号 JP20080205271 申请日期 2008.08.08
申请人 FDK CORP 发明人 MASUNO HIROSHI;KAWAI TATSUJI
分类号 H01F17/00;H01F41/04 主分类号 H01F17/00
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