CMOS IMAGE SENSOR WITH SELECTABLE HARD-WIRED BINNING

摘要

A CMOS image sensor allows for selectively outputting one of two vertical resolutions, e.g. 1080 to 720 lines. The scan conversion is implemented completely on the image sensor chip by using smaller sub-pixel cores, which can be electrically combined via switch transistors. A basic circuit of the CMOS image sensor has a number of pixel cells arranged in lines and columns. Each pixel cell has a photosensitive element that converts impinging light into electric charge and a first transfer element. The first transfer elements of m pixel cells arranged consecutively in the same column are arranged for transferring the charge generated in the respective m photosensitive elements during exposure to a single first charge storage element provided for the respective group of m pixel cells. In an exemplary embodiment the switching scheme allows for combining the signal information of either two or three vertically adjacent sub-pixel cores.