| 摘要 |
<P>PROBLEM TO BE SOLVED: To speed up control operation of a PLC equipped with a low speed backup RAM. Ž<P>SOLUTION: This PLC is provided with an EPGA 10 interposed among a CPU 4a, a high speed RAM 4b, and a backup RAM 9, and the FPGA 10 writes backup data to be transmitted from the CPU 4a one after another in the high speed RAM 4b, and erases the data. Thus, the high speed writing of backup data is achieved. On the other hand, the successive copying of the backup data successively written in the high speed RAM 4b, to the backup RAM 9 before erasures according to the speed is controlled. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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