发明名称 SCAN TEST CIRCUIT, LOGICAL CONNECTION INFORMATION GENERATING METHOD OF THE SAME, AND PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To solve a problem wherein the test time of a scan test increases even if the occurrence of voltage drop (IR drop) of a power supply line is suppressed during a scan test of a semiconductor integrated circuit. Ž<P>SOLUTION: The scan test circuit includes scan sub-chains, a scan chain selection circuit, and scan shift input terminals. Each of the scan sub-chains belonging to the same first kind of groups is connected to a different scan shift input terminal, and each of the scan sub-chains belonging to different first kind of groups is connected to one scan shift input terminal in parallel. The scan chain selection circuit controls the scan sub-chains so that the scan sub-chains for simultaneously performing scan operation belong to any first group. Even when all of the scan sub-chains belonging to the same first kind of groups simultaneously perform scan operation, allowance of the IR drop is satisfied. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010038874(A) 申请公布日期 2010.02.18
申请号 JP20080205514 申请日期 2008.08.08
申请人 NEC ELECTRONICS CORP 发明人 KIRIAKI WATARU
分类号 G01R31/28;G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G01R31/28
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