| 摘要 |
<p>An image display apparatus has an A/D converter (1) for sampling an analog video signal (R,G,B) whose signal level changes at a frequency higher than the frequency of a synchronizing signal, based on a reproduced dot clock (M_CLK), and converting the sampled analog video signal into a digital video signal, a clock adjusting circuit (4) for generating a clock in synchronism with the synchronizing signal, delaying the phase of the clock according to set delays, and outputting the delayed clock as the reproduced dot clock (M_CLK), a controller (6) for dividing an area of an image displayed based on the converted digital video signal, into a plurality of image areas defined by display lines in a horizontal direction, and establishing different delays for the divided image areas, and a delay evaluating circuit (3) for converting differential data between adjacent signal levels on the display lines for the respective image areas, into absolute values and accumulatively adding the absolute values, thereby producing accumulated sums. The controller (6) judges the delay established for the divided area with the maximum accumulated sum, as an optimum delay.</p> |
