| 摘要 |
<p>An object of the present invention is to achieve both suitable timing design and a high yield even when delay of an element or wiring varies in an asynchronous circuit subjected to a relative delay restriction. A circuit design device (100) comprises a logic synthesis unit (111) that generates a circuit with reference to a circuit design description, a statistical timing analysis unit (112) that obtains a probability distribution of delay times of a path in a circuit, a relative delay restriction fulfillment rate calculation unit (113) that obtains a fulfillment rate of the relative delay restriction according to the probability distribution of the delay time from the same starting point at each restricted path subjected to the relative delay restriction, a path delay probability distribution changing unit (117) that changes the probability distribution of delay times of the restricted path to changed probability distribution when the fulfillment rate does not reach a predetermined rate, and a logic circuit structure changing unit (114) that changes the structure of the circuit so as to follow the changed probability distribution ( FIG. 1 ).</p> |
