WAFER LEVEL CHIP SCALE PACKAGE AND FABRICATING METHOD OF THE SAME

摘要

PURPOSE: A wafer level chip scale package and a manufacturing method thereof are provided to alleviate the stress concentration generating in a junction part by forming a release coating part on an area except for a solder ball. CONSTITUTION: A semiconductor chip comprises a bonding pad(102) on the upper side. An insulating layer(104) is formed on the upper side of the semiconductor chip except for the bonding pad. One end of a rerouting layer(106) is connected to the bonding pad on the insulating layer, and the other end has the rerouting layer. The solder resist layer is formed on the redistribution layer except for the connection pad and insulating layer. A first solder ball(110) is formed on the connection pad. A release coating part(111) is formed on the exterior of the first solder ball projected to the solder resist layer. A resin encapsulation part(112) is formed to include the first solder ball so that the redistribution layer and solder resist layer can be combined.