发明名称 |
Method for performing post-synthesis circuit optimization |
摘要 |
Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by using interior point optimization methods. The first method treats gate delays as uncertain quantities and obtains the optimal sizes for gates in a circuit under a probabilistically specified circuit timing target. The second method optimizes total circuit power by using a combination of dual threshold voltage assignment and gate sizing. Both circuit power and timing are treated probabilistically.
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申请公布号 |
US7665047(B2) |
申请公布日期 |
2010.02.16 |
申请号 |
US20060539671 |
申请日期 |
2006.10.09 |
申请人 |
ORSHANSKY MICHAEL;MANI MURARI |
发明人 |
ORSHANSKY MICHAEL;MANI MURARI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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