发明名称 FAILURE ANALYSIS METHOD AND FAILURE ANALYZER OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a failure analysis method, analyzer and an analysis program of a semiconductor integrated circuit capable of specifying easily a physical failure cause to a detection signal acquired from the analyzer, relative to failure analysis of the semiconductor integrated circuit. Ž<P>SOLUTION: A physical defect in a semiconductor wafer is inspected by visual inspection or the like when manufacturing a semiconductor integrated circuit chip (S1), and a logical operation test of the semiconductor integrated circuit chip is performed to extract a malfunctioning chip (S2), and a detection signal observed from the malfunctioning chip is analyzed by the analyzer, to thereby acquire a coordinate and a layer from which a detection signal is detected (S3). A layer and a coordinate of a circuit connected to a cell or a net from which the detection signal is detected are determined by using design data and the coordinate and the layer of the detection signal (S4), and a physical defect related to the circuit is specified by comparing the layer and the coordinate of the circuit with an inspection process in which the physical defect is detected and the chip inside coordinate of the physical defect (S5). Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010032295(A) 申请公布日期 2010.02.12
申请号 JP20080193312 申请日期 2008.07.28
申请人 NEC ELECTRONICS CORP 发明人 NIKAIDO MASATO
分类号 G01R31/302 主分类号 G01R31/302
代理机构 代理人
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