PLL CIRCUIT, AND COMMUNICATION APPARATUS AND LOOPBACK TEST METHOD THEREOF

摘要

PROBLEM TO BE SOLVED: To provide a PLL circuit including a spread spectrum clocking (SSC) generating function capable of smoothly shifting a modulation degree of the SSC while suppressing jitter of the SSC.

SOLUTION: An SSC controller 18 controls a phase interpolator 15 so as to change a phase shift amount in timing predetermined in accordance with a modulation profile of the SSC and periodically changes a modulation degree of an output clock signal C_OUT. Further, the SSC controller 18 controls a total phase shift amount to be applied to a phase shift signal C_PS output from the phase interpolator 15 within one term of a feedback clock signal C_FB such that a differential between the total phase shift amount and a total phase shift amount of preceding one term can become not more than a fundamental delay amount Δ at all the time, wherein the fundamental delay amount Δ is a value dividing a term T_OUT of the output clock signal C_OUT by a phase resolution Nr of the phase interpolator 15 (that is T_OUT/Nr).

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