DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNED BY THE DESIGNING METHOD

摘要

<P>PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor integrated circuit by suppressing inter-wiring interference of the semiconductor integrated circuit. Ž<P>SOLUTION: In a step A1, a CAD system 10 generates a net list. In a step A2, a circuit simulator 13 performs DC analysis of the whole semiconductor integrated circuit based upon the net list to calculate operation points thereof, and performs AC analysis of all nodes included in the semiconductor integrated circuit in sequence based upon the operation points and the net list to output impedance information on each node to an impedance determination unit 14. The impedance determination unit 14 specifies a node having an absolute value ¾Z¾ of an impedance vector larger than a predetermined threshold. In a step A4, wiring connected to the predetermined node is displayed as wiring which may induce inter-wiring interference on a display 12 discriminatingly from other wiring. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž