发明名称 HIGH VOLTAGE INPUT RECEIVER WITH HYSTERESIS USING LOW VOLTAGE TRANSISTORS
摘要 A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.
申请公布号 US2010033214(A1) 申请公布日期 2010.02.11
申请号 US20080188227 申请日期 2008.08.08
申请人 DESHPANDE VANI;IYENGAR ANUROOP;PARAMESWARAN PRAMOD ELAMANNU;KUMAR PANKAJ 发明人 DESHPANDE VANI;IYENGAR ANUROOP;PARAMESWARAN PRAMOD ELAMANNU;KUMAR PANKAJ
分类号 H03K5/24 主分类号 H03K5/24
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