发明名称 AREA EFFICIENT 3D INTEGRATION OF LOW NOISE JFET AND MOS IN LINEAR BIPOLAR CMOS PROCESS
摘要 Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.
申请公布号 US2010032728(A1) 申请公布日期 2010.02.11
申请号 US20090537352 申请日期 2009.08.07
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 HAO PINGHAI;DENISON MARIE
分类号 H01L27/12;H01L21/762;H01L29/78 主分类号 H01L27/12
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