Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors

摘要

A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. Some of the conductive features form respective PMOS and/or NMOS transistor devices. The cell includes an equal number of PMOS and NMOS transistor devices. The cell also includes a number of interconnect levels formed above the gate electrode level.