PHASE COMPARATOR, PLL CIRCUIT, AND DLL CIRCUIT

摘要

A phase comparator which allows solution of the problem that a phase difference cannot be discriminated, while suppressing increase in power consumption and a circuit area. A variable delay circuit (3) adjusts the phase of a signal (f2) to generate a delay signal (f2'). A binary phase comparator (4) discriminates the front/rear relation between the phase of a signal (f1) and that of the delay signal (f2'), and outputs the discrimination result showing the front/rear relation. A control logic circuit (9) adjusts the delay amount of the variable delay circuit (3) on the basis of the discrimination result, and determines a weight value to be imparted to the discrimination result according to the adjusted delay amount. A weighting circuit imparts the determined weight value to the discrimination result. An output part outputs the discrimination result to which the weighting circuit imparts the weight value, as error signals showing the front/rear relation between the phase of the signal (f1) and that of the signal (f2) and the phase difference between the signals (f1 and f2).