发明名称 Through Silicon Via Layout
摘要 A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.
申请公布号 US2010032843(A1) 申请公布日期 2010.02.11
申请号 US20080186105 申请日期 2008.08.05
申请人 CHEN MING-FA;CHEN CHEN-SHIEN 发明人 CHEN MING-FA;CHEN CHEN-SHIEN
分类号 H01L23/498 主分类号 H01L23/498
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