发明名称 Method and apparatus for testing electronic components within horizontal and vertical boundary lines of a wafer
摘要 A method and an apparatus are provided which make it possible, when testing chips arranged on a wafer, to be able to test optionally both additional components arranged on horizontal boundary lines and on vertical boundary lines. The additional components arranged on horizontal boundary lines are tested in a first position of the wafer. For testing the additional components arranged on vertical boundary lines, the wafer is rotated about its vertical axis through 90° relative to the first position into a second position. The apparatus comprises a housing and, in the housing, at least one test probe for making contact with an electronic component, a chuck for moving the wafer and a rotatably mounted additional plate operatively connected to the chuck.
申请公布号 US7659743(B2) 申请公布日期 2010.02.09
申请号 US20070947206 申请日期 2007.11.29
申请人 SUSS MICROTEC TEST SYSTEMS GMBH 发明人 KANEV STOJAN;KIESEWETTER JOERG
分类号 G01R31/02 主分类号 G01R31/02
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