发明名称 System and method for abstraction refinement verification
摘要 An apparatus and methods for the verification of digital design descriptions are provided. In an exemplary embodiment, a method of verifying a property in a digital design description is provided. The method includes deriving an abstraction of the digital design description, determining a counterexample by an approximate reachable state computation, justifying the counterexample, determining a justification frontier, updating the abstraction from the justification frontier, and producing a verification result for the digital design description. One feature of this embodiment is that it provides for efficient digital circuit verification. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
申请公布号 US7661082(B1) 申请公布日期 2010.02.09
申请号 US20070692802 申请日期 2007.03.28
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 MCMILLAN KENNETH L.;AMLA NINA
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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