| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device for facilitating design of wiring between a plate line and each memory block and wiring of bit lines, and which is suitable for downsizing. Ž<P>SOLUTION: In the semiconductor memory device, a cell transistor and a ferroelectric capacitor connected in parallel configure a cell, cells connected in series configure first to eighth cell blocks. The cell blocks are connected to the same word line, one end of the cell block is connected to a bit line through a block selection transistor, the other end of the cell block is connected to different plate lines. During operation, one of first to fourth bit lines and one of fifth to eighth bit lines are connected selectively to a sense amplifier, numbers of memory cells connected in series between the bit line and the plate line are different in the first to the fourth memory cell blocks, and are different in the fifth to the eighth memory cell blocks. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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