发明名称 CIRCUIT AND METHOD FOR SPECIFYING FAULTY FLIP-FLOP IN SCAN CHAIN
摘要 PROBLEM TO BE SOLVED: To provide a faulty flip-flop specification method capable of specifying faulty flip-flop candidates not more than two without increasing the number of pins and wiring regions in a faulty flip-flop specification circuit of a scan chain. SOLUTION: The faulty flip-flop specification circuit 100 of a scan chain which includes: a scan input pin 02 for inputting scan signals; a reset input pin 04 for inputting reset signals; a clock pin for inputting clocks; and a plurality of flip flops and a scan output pin 06, inputs a reset signal from the reset input pin 04 connected to respective reset terminals of all flip flops, inputs an inverted output signal to the scan input terminal of a flip flop at the next stage connected from respective QN terminal of flip flops corresponding to the input of clock signals, and outputs a scan signal to the scan output pin 06 connected to a QN terminal 58 of the flip flop in the final stage. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010025903(A) 申请公布日期 2010.02.04
申请号 JP20080191143 申请日期 2008.07.24
申请人 OKI SEMICONDUCTOR CO LTD 发明人 USHIKUBO MASANORI
分类号 G01R31/28 主分类号 G01R31/28
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