发明名称 THREAD COMPLETION RATE CONTROLLED SCHEDULING
摘要 A method, processor and processing system provide management of per-thread pipeline resource allocation in a simultaneous multi-threaded (SMT) processor by counting indications of instruction completion for each of the threads. The indication may be the commit phase of the pipeline, which indicates results of the pipeline instruction execution are ready for write-back. The completion counts are used in a relative or absolute form to control the pipeline resource allocation. The decode or fetch rates of instructions for the threads can be controlled from the relative or absolute completion counts, providing control of scheduling instructions among the threads for execution by execution pipeline(s). Alternatively, or in combination, the thread priority registers in any thread priority management scheme can be controlled by comparison and/or scaling of the completion counts.
申请公布号 US2010031006(A1) 申请公布日期 2010.02.04
申请号 US20080185206 申请日期 2008.08.04
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 EL-ESSAWY WAEL R.;ZHANG LIXIN
分类号 G06F9/30 主分类号 G06F9/30
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