Memory test circuit which tests address access time of clock synchronized memory

摘要

A circuit for testing an access time of a clock synchronization type memory, includes a delay circuit, a sampling circuit and a coincidence detection circuit. The delay circuit generates a delayed clock obtained by delaying, by a time acceptable for a memory performance, a clock inputted to a memory. The sampling circuit takes in and outputs an output from the memory at the timing of the delayed clock. The coincidence detection circuit detects coincidence or non-coincidence by comparing the output from the sampling circuit with an expected value for the output from the memory.