发明名称 LAMINATED CHIP VARISTOR, AND METHOD OF MANUFACTURING THE SAME
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a laminated chip varistor that suppresses deposition of plating metal on a part other than a part where a terminal electrode is formed while protecting a surface of a blank body, and to provide a method of manufacturing the same. <P>SOLUTION: The laminated chip varistor 1 includes the blank body 2 consisting principally of a semiconductor, the terminal electrode 8 formed on the blank body 2, a high-resistance layer 5 formed as a surface layer of the blank body 2 at least other than the part where the terminal electrode 8 is formed and containing alkali metal, and a glass layer 6 formed on the high-resistance layer 5. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010027804(A) 申请公布日期 2010.02.04
申请号 JP20080186399 申请日期 2008.07.17
申请人 TDK CORP 发明人 KAJINO TAKASHI;ABE TOSHIYUKI
分类号 H01C7/10;H01C7/00 主分类号 H01C7/10
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