SEMICONDUCTOR MEMORY DEVICE

摘要

A control circuit (11) supplies a word line driving voltage (WD1) to a word line (WL1) corresponding to a write target memory cell (MC1) among word lines (WL1, WL2) in a word line driving period containing a first period and a second period following the first period, decreases the current capabilities of load transistors (QLa, QLb) included in the write target memory cell (MC1) in the first period, and increases the current capabilities of the load transistors (QLa, QLb) included in the write target memory cell (MC1) in the second period.