发明名称 SYSTEM AND METHOD FOR FETCHING INFORMATION TO A CACHE MODULE USING A WRITE BACK ALLOCATE ALGORITHM
摘要 <p>A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.</p>
申请公布号 WO2010014282(A1) 申请公布日期 2010.02.04
申请号 WO2009US42021 申请日期 2009.04.29
申请人 FREESCALE SEMICONDUCTOR INC.;GODIN, KOSTANTIN;LANDA, ROMAN;PELED, ITAY;T0KAR, YAKOV;ZAMSKY, ZIV 发明人 GODIN, KOSTANTIN;LANDA, ROMAN;PELED, ITAY;T0KAR, YAKOV;ZAMSKY, ZIV
分类号 G06F13/32;G06F12/00;G06F13/28;G06F13/38 主分类号 G06F13/32
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