| 摘要 |
<P>PROBLEM TO BE SOLVED: To effectively suppress any influence of cache miss, in a processor for simultaneously executing a plurality of programs. Ž<P>SOLUTION: In a processor for simultaneously executing a plurality of programs, instruction words of first and second programs are read from a main storage device or a cache, and the read instruction words are queued in a first storage means. The second and third storage means respectively store execution cycle estimation information for estimating the number of cycles required for executing the instruction words included in the first and second programs, and the first and second cache error predictors respectively read the estimation information of the number of execution cycles. The scheduling positions of the instruction words are determined according to the content of the execution cycle estimation information. It is desired that the execution cycle estimation information is dynamically changed according to whether the cache miss is detected or not. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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