| 摘要 |
<p>Integrated circuit comprising a substrate carrying at least one transistor comprising an alternating grid (1) of source and drain regions (D, S) separated by a grid (14) of gate regions, e.g. a checkerboard pattern of source and drain regions. The source regions (S) are vertically connected to a first metal layer and the drain regions (D) are vertically connected to a second metal layer. At least one of the first metal layer and the second metal layer comprises a metal grid (30, 40) of a plurality of interconnected metal portions (32, 42) arranged such that said grid comprises a plurality of gaps (34, 44) for connecting respective substrate portions to a further metal layer. Method for manufacturing such an integrated circuit.</p> |
