| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory test circuit that executes a memory test during operation of a computer system and without providing an area exclusive for a memory test. Ž<P>SOLUTION: The memory test circuit is composed of a memory array part 11, which has a test-target memory area 11c being a target of a memory test and writes a first test pattern outputted from an array test circuit 20 to the test-target memory area 11c, a redundant array part 12 being a save destination of data recorded in the test-target memory area 11c, an array test circuit 20, which outputs save-area address information and the first test pattern to the memory array part 11 and compares the first test pattern with a second test pattern outputted from the memory array part 11 after writing them to the memory array part 11, and an operational circuit 30 for outputting a memory-test start signal to the array test circuit 20. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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